
![[Pentium vs P6]](../../v2gr/v2gr_hw/hwcmin61.gif)
![[Intel P6]](../../v2gr/v2gr_hw/hwcmin6.gif)
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- Design significantly different than the Pentium.
- Available at 150MHz, 166MHz, 180MHz and 200MHz core speeds
- Binary compatible with applications running on previous members of the Intel
microprocessor family
- Optimized for 32-bit applications running on advanced 32-bit operating systems
- Dynamic Execution microarchitecture (Instructions processed using dynamic execution
(simultaneously chops up x86 instructions into sets of micro instructions, processing what
it can and queuing the rest until the necessary data becomes available. Once a complete
instruction is processed, the P6 reassembles the instruction and carries out the action. )
- To keep the chip processing, speculative execution and branch prediction also used to
make a best guess at which instructions and data will be required to perform an operation
- Single package includes Pentium® Pro processor CPU, cache and system bus interface
- Chip contains two cavities
- one for the processor
* 32 bit processor has 5.5 million transistors (Pentium 3.1 million)
* 2 x 8Kb caches one for data one for instructions
- one for secondary cache
* 256Kb operating at the same speed as the processor
Scalable up to four processors and 4 GB memory
Separate dedicated external system bus, and dedicated internal full-speed cache bus
8K/8K separate data and instruction, non-blocking, level one cache
Leve 2 Cache: 256 KB, 512 KB or 1 MB non-blocking.
Data integrity and reliability features include ECC, Fault Analysis/Recovery, and
Functional Redundancy Checking
Intel estimates P6 will find data 90% of the time in either primary or secondary cache
387 pins running at 3.1Volts (150MHz) and 3.3 Volts
64 bit external bus (like the Pentium), that can operate at one-half, one-third or
one-quarter CPU speed.
Architecture resembles that of AMD's K5.
Intel (1998, Feb) Ref:
[111]NZ PC World May '95
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